Digital communication receivers must sample an analog waveform and then reliably detect the sampled data. Signals arriving at a receiver are typically corrupted by intersymbol interference (ISI), crosstalk, echo, and other noise. Thus, receivers must both equalize the channel, to compensate for such corruptions, and detect the encoded signals at increasingly higher clock rates. Decision-feedback equalization (DFE) is a widely used technique for removing intersymbol interference and other noise. For a detailed discussion of decision feedback equalizers, see, for example, R. Gitlin et al., Digital Communication Principles, (Plenum Press 1992) and E. A. Lee and D. G. Messerschmitt, Digital Communications, (Kluwer Academic Press, 1988), each incorporated by reference herein in their entirety.
Generally, decision-feedback equalization utilizes a nonlinear equalizer to equalize the channel using a feedback loop based on previously detected (or decided) data. In one typical DFE implementation, a received analog signal is sampled after DFE correction and compared to one or more thresholds to generate the detected data. The DFE correction, v(t), is subtracted in a feedback fashion to produce a DFE-corrected signal w(t). A clock, generated from the received signal by a Clock and Data Recovery (CDR) circuit, is generally used to sample the DFE-corrected signal and for the DFE operation. Typically, the entire DFE loop correction must be performed within one baud-period T of the received signal before the next correction is needed. At very high data rates, however, it is difficult to design circuits that operate this fast or to make them very accurate. Consequently, a number of techniques have been proposed or suggested for eliminating the DFE feedback loop by using precomputed the DFE terms in an “unrolled” DFE architecture. Since there is no DFE feedback loop, the process of generating the DFE “corrected” detections can be pipelined. In such a DFE precomputation implementation, the DFE correction is not fed back to correct the received signal, making the input to the CDR circuit non-DFE detected data. Thus, the CDR circuit processes unequalized data that still contains channel impairments.
An improved receiver is disclosed in “Method and Apparatus for Generating One or More Clock Signals for a Decision-Feedback Equalizer Using DFE Detected Data”, by Aziz et al, U.S. Pat. No. 7,616,686, incorporated by reference herein in its entirety, utilizes a DFE-based phase detection architecture for clock and data recovery of a DFE equalized signal. The disclosed architecture effectively generates one or more clock signals for the decision-feedback equalizer using DFE detected data and DFE transition data. However, it has been observed that, under certain conditions, the generator of the clock signals can produce additional clock jitter. It is believed that the DFE correction to transition samples used by the CDR to generate the various clocks is one source of the increase in clock jitter. In particular, the jitter performance of the phase detector in the clock generator has been found to be dependent on the DFE delay. Thus, it is desirable to provide a phase detector that corrects for the DFE delay.